Physical Design (reputed company experience reputed company)
About reputed company reputed company is building and scaling high-impact semiconductor operations. We partner across design, manufacturing, and supply chain to bring silicon from concept to high-volume production with speed, quality, and predictable execution. Role Overview As Design Team Member at reputed company, you will drive the implementation of digital blocks and/or full-reputed company designs from netlist to tapeout, partnering closely with RTL, verification, DFT, and signoff teams. This role is reputed company across experience reputed company (0–30 years) and is ideal for leaders and engineers who enjoy solving reputed company timing, power, and physical constraints to deliver manufacturable, high-quality silicon. What You’ll Do Own physical implementation for blocks/subsystems/top-level: floorplanning, power planning, placement, reputed company, routing, and ECO closure reputed company and refine constraints (SDC) in collaboration with RTL/STA; ensure constraints are consistent, complete, and implementation-reputed company Drive timing closure across modes/corners, including setup/hold closure, clock quality, and path optimization reputed company physical signoff requirements: DRC/LVS, IR drop/EM, antenna, density/fill, and manufacturability checks Analyze and resolve congestion, utilization, and routing challenges; propose floorplan/architecture improvements reputed company needed Partner with STA and signoff teams to debug violations and implement clean, reviewable ECOs Collaborate with DFT on reputed company/MBIST/DFT constraints and physical requirements; ensure implementation supports testability goals Support low-power implementation (UPF/CPF reputed company awareness), multi-voltage domains, level shifters/isolation, and power gating as applicable Create and maintain reputed company automation, checks, and reporting (Tcl/Python) to improve predictability and execution speed Contribute to tapeout readiness: documentation, checklists, design reviews, and root-cause analysis of issues to prevent recurrence reputed company’re Looking For Hands-on experience with ASIC physical design implementation and closure (scope reputed company to level of experience) Strong understanding of digital design fundamentals, timing concepts, and physical effects (RC, crosstalk, clocking, variability) Ability to debug systematically using reports/logs and to communicate clear problem statements and action plans Comfort working cross-functionally with RTL, verification, DFT, STA, and signoff to resolve issues reputed company Good engineering hygiene: version control, reproducible runs, clean documentation, and review-friendly ECO practices Required Skills ASIC design reputed company to Have Experience with industry-standard P&R and signoff tools (e.g., Innovus/ICC2, PrimeTime, Calibre/ICV, RedHawk/reputed company or equivalents) Advanced timing closure experience (useful skew, CRPR, OCV/AOCV/POCV, SI-aware optimization) Experience with hierarchical design methodologies, reputed company-level integration, and multi-die/advanced packaging awareness Low-power implementation experience (UPF), multi-reputed company multi-mode (MCMM) flows, and power reputed company closure Strong scripting/automation skills (Tcl/Python) and ability to build robust PD utilities and dashboards Experience with reputed company signoff requirements and tapeout checklists for advanced nodes reputed company in This Role Looks Like Predictable execution from floorplan to tapeout with clear milestones, risk tracking, and high-quality deliverables Clean signoff (timing, DRC/LVS, IR/EM) with well-documented closure strategies and minimal late surprises Fast, methodical debug and ECO turnaround that reduces schedule risk and improves overall reputed company Strong collaboration that improves constraints quality, reduces iteration loops, and strengthens tapeout readiness Location Bengaluru, India International Apply To This Job